View ZL10210_295826.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ZL10210
DVB-C Cable Channel Demodulator
Data Sheet Features
* * * * * * * * * * * * * * * * * * * DVB-C EN300429 and ITU-T J.83 annex A/C compliant QAM demodulator Conventional IF and low IF input supported QAM constellations 16, 32, 64, 128 and 256 Symbol rates up to 9 MBaud Blind acquisition of all symbol rates Blind acquisition of QAM constellations Single IF filter bandwidth for all symbol rates Signal level, BER and SNR indicators Programmable IF/RF AGC take-over point Power down mode under software control Parallel and serial MPEG outputs External 4 or 27 MHz clock or single low-cost 10 MHz crystal Small package size LQFP64 7x7 mm Power consumption <300 mW at 6.9 MBaud 5 V tolerant 2-wire bus control interface 5 V tolerant GPIO port and AGC outputs RF level detect facility via a separate ADC Very low driver software overhead due to on-chip state-machine control. General purpose programmable timer -40oC to +85oC Ordering Information ZL10210/GC/GP1N 64 Pin LQFP
November 2005
Description
The ZL10210 is a DVB-C and ITU-T annex A/C QAM demodulator. This low power cable demodulator includes standard Zarlink features of auto signal acquisition, fast blind-scan capability, software/hardware power down, RF level, BER and SNR detection. The ZL10210 represents the latest in QAM demodulation for DVB cable. Together with a cable tuner, a full digital cable receiver front-end can be realized. Either conventional intermediate frequencies such as 36 or 44 MHz or low intermediate frequencies can be used see application below. The ZL10210 requires only a single channel filter bandwidth of 8 MHz nominal for full DVB and ITU-T annex A/C performance. The low power consumption, small package form factor and integrated software/hardware power-down modes help reduce the system BoM (bill of materials) in cost sensitive applications. The device is packaged in a 7 x 7 mm 64-pin LQFP.
Applications
* * * * Set-top boxes Digital cable ready TV applications Cable modems SMATV/MATV receivers
Functional Description
The ZL10210 accepts an analog signal from the tuner, either at low Intermediate Frequency (IF) or conventional IF up to 50 MHz, and delivers an MPEG2 compliant transport stream. It contains a single 10-bit
Figure 1 - System Diagram 1
Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2005, Zarlink Semiconductor Inc. All Rights Reserved.
ZL10210
Data Sheet
analog-to-Digital Converter (ADC), a digital QAM demodulator and Forward Error Correcting (FEC) decoder. The QAM demodulator supports QAM constellations 16 to 256. Both the QAM demodulator and the FEC are DVB and ITU-T J.83 annex A/C compliant.
Figure 2 - ZL10210 Functional Diagram The ADC uses a fixed sample rate greater than four times the maximum symbol rate. Hence for 1 to 9 MBaud applications, the signal has to be sampled at a frequency around 36 MHz. The spectrum of the analog signal being sampled may be located at near-zero IF (e.g. centered at 9 MHz) or it may be located at a conventional IF such as 36.2 MHz or 43.5 MHz. First consider the case of IF sampling a 1 to 7 MBaud QAM signal centered at 36.2 MHz intermediate frequency. The sampling frequency chosen for this application is 28.9 MHz. This sampling process will fold the 36.2 MHz IF spectrum to one centered at 7.3 MHz. Second consider the case of IF sampling a 1 to 6 MBaud QAM signal centered at 43.5 MHz IF. The sampling frequency chosen for this application is 25 MHz. This sampling process will result in a QAM spectrum centered at 6.5 MHz. In the second case the sampling process results in spectral inversion. Even in first case the IF spectrum may be spectrally inverted. However, spectral inversion is not an issue with ZL10210 since it automatically detects and corrects for this in the digital domain. The digital signal is first mixed down to baseband. However, as a result of tuning errors this signal will not be centered at zero frequency. ZL10210 has an automatic frequency control (AFC) loop that can track out tuning errors and hence in the tracking phase this signal will be centered at zero frequency. The AFC loop can typically compensate for +/-350 kHz frequency offsets. Larger offsets can be corrected by programming on-chip registers. The baseband signal is filtered to reduce the effect of adjacent channels. Additional on-chip digital filtering is provided for low symbol rate applications. For example, it is possible to demodulate and decode a 1 MBaud QAM signal using only one external 8 MHz SAW filter.
2
Zarlink Semiconductor Inc.
ZL10210
Data Sheet
ZL10210 has complete blind acquisition capability. It can automatically search and lock on to any QAM constellation in the set 16, 32, 64, 128 and 256. It can compensate for spectral inversion. It can also automatically acquire a symbol rate in the range 1 to 7 MBaud correcting for any tuning errors and adapting the filter bandwidths to signal bandwidth. All these functions are implemented using a sophisticated built-in control state machine with no software intervention. The symbol-spaced equalizer in the ZL10210 is designed to acquire the QAM signal in blind mode, i.e., with no training sequence, and then to track the signal in the decision feedback mode. The equalizer has a feed-forward segment and a feedback segments. The tap partitioning between feed-forward and feedback is fully programmable. The symbol timing and phase recovery functions with the ZL10210 are fully digital. The timing recovery phase locked loop has a built in timing sweep to enable the ZL10210 to lock on to unknown symbol rates. The phase recovery loop has been optimised to overcome phase noise degradation caused by typical tuners. The ZL10210 QAM demodulator has built in control mechanisms to overcome signal degradation due to impulse noise in cable systems. The most significant bits of the demodulated I/Q symbols are differentially decoded to remove multiples of 90 degree phase ambiguity in demodulation. The QAM symbols are then demapped into a bit stream, using the constellation definitions provided by DVB and ITU-T. The number of bits per symbol is eight for QAM-256, seven for QAM-128, six for QAM-64, five for QAM-32 and four for QAM-16. The bitstream is aligned into bytes and then into 204-byte frames by the Frame Alignment Unit. These frames are deinterleaved as defined by DVB to improve the resilience of the system to error bursts. The (204,188) ReedSolomon decoder, which follows the deinterleaver, can correct up to eight byte-errors per frame. This also generates an uncorrectable error flag for blocks with more than eight byte-errors. In addition, the ZL10210 ReedSolomon decoder keeps a count of the number of uncorrectable blocks and the number of bit errors corrected. The former will give an indication on the quality of the MPEG output and the latter provides the Bit Error Rate in QAM demodulation. The decoder packets are then descrambled to reverse the energy dispersal function introduced by the transmitter. The output of the device is a stream of regularly spaced MPEG packets. The MPEG byte clock frequency is automatically adapted to be the minimum needed for a given symbol rate and QAM constellation. Alternatively the MPEG bytes can be clocked out using an externally provided byte clock. There is also an option for bit-serial output.
3
Zarlink Semiconductor Inc.
ZL10210
Data Sheet
Figure 3 - Typical ZL10210 Application
4
Zarlink Semiconductor Inc.
ZL10210 1.0
1.1
Data Sheet
Pin & Package Details
Pin Outline
Figure 4 below shows the pin functions of the ZL10210.
Figure 4 - Pin Outline
1.2
Pin 1 2 3 4 5 6 7 8
Pin Allocation
Function Vdd CVdd Gnd SADD3 SADD2 IRQ CVdd Gnd Pin 17 18 19 20 21 22 23 24 Function GPP0 SADD4 RESET SLEEP PLLTest PLLVdd Gnd XTI Pin 33 34 35 36 37 38 39 40 Vdd RFLev Gnd CVdd SADD1 SADD0 AGC2/GPP1 AGC1 Function Pin 49 50 51 52 53 54 55 56 Function MDO0 MDO1 MDO2 MDO3 MDO4 MDO5 Vdd Gnd
Table 1 - Pin Names - numeric
5 Zarlink Semiconductor Inc.
ZL10210
Pin 9 10 11 12 13 14 15 16 Function CLK1 DATA1 CVdd Gnd SMTest STATUS Gnd Vdd Pin 25 26 27 28 29 30 31 32 Function XTO Gnd OSCMode AVdd Gnd VIN VIN Gnd Pin 41 42 43 44 45 46 47 48 Gnd CVdd Vdd Gnd CLK2 DATA2 MOSTRT MOVAL Function Pin 57 58 59 60 61 62 63 64
Data Sheet
Function CVdd Gnd MDO6 MDO7 MOCLK
BKERR
MICLK Gnd
Table 1 - Pin Names - numeric (continued)
Function
AGC1 AGC2/GPP1 AVdd
Pin
40 39 28 62 9 45 2 7 11 36 42 57 10 46 3 8
Function
Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd GPP0
Pin
12 15 23 26 29 32 35 41 44 56 58 64 17 6 49 50
Function
MDO2 MDO3 MDO4 MDO5 MDO6 MDO7 MICLK MOCLK MOSTRT MOVAL OSCMode PLLTest PLLVdd
Pin
51 52 53 54 59 60 63 61 47 48 27 21 22 19 34 38
Function
SADD1 SADD2 SADD3 SADD4 SLEEP SMTest STATUS Vdd Vdd Vdd Vdd Vdd VIN
Pin
37 5 4 18 20 13 14 1 16 33 43 55 30 31 24 25
BKERR
CLK1 CLK2 CVdd CVdd CVdd CVdd CVdd CVdd DATA1 DATA2 Gnd Gnd
IRQ
MDO0 MDO1
RESET
RFLev SADD0
VIN XTI
XTO
Table 2 - Pin Names - alphabetical order
6 Zarlink Semiconductor Inc.
ZL10210
1.3 Pin Description
Data Sheet
Pin Description Table
Pin No MPEG pins 47 48 49-54, 59-60 61 62 63 14 6 Control pins 9 10 24 25 20 4, 5,18,37,38 13 45 46 40 39 17 19 CLK1
Name
Pin Description
I/ O
Type
V1
mA
MOSTRT MOVAL MDO(0:5) MDO(6:7) MOCLK BKERR MICLK STATUS IRQ
MPEG packet start MPEG data valid MPEG data outputs MPEG output clock Block error output MPEG input clock Status output Interrupt output
O O O O O I O O Open drain CMOS CMOS Tristate
3.3 3.3 3.3 3.3 3.3 3.3 3.3 5
1 1 1 1 1
1 6
Serial clock Serial data Low phase noise crystal oscillator
I I/ O I I/ O I I I I/ O I/ O O I/ O I/ O I
CMOS Open drain CMOS
5 5 1.8 1.8 5 3.3 3.3 6
DATA1 XTI XTO SLEEP SADD(4:0) SMTest CLK2 DATA2 AGC1 AGC2/GPP1 GPP0 RESET
Device power down Serial address set Production test (only set low) Serial clock tuner Serial data tuner Primary AGC Secondary AGC or general I/O General purpose I/O Device reset - active low
Open drain
5 5 5 5 5
6 6 6 6 6
CMOS
5
7 Zarlink Semiconductor Inc.
ZL10210
Pin Description Table (continued)
Data Sheet
Pin No 27
Name OSCMode
Pin Description Crystal oscillator mode: Low = crystal oscillator High = external clock PLL test - do not connect
I/ O I
Type CMOS
V1 3.3
mA
21 Analog inputs 30 31 34
PLLTest
O
(tristated)
VIN VIN
ADC positive input ADC negative input RF level ADC input
I I
Analog input nominally 400 mV AC coupled Analog input nominally 3.3 V for max. level
3.3
RFLev
I
Supply pins 28 2, 7, 11, 36, 42, 57 22 1, 16, 33, 43, 55 3, 8, 12, 15, 23, 26, 29, 32, 35, 41, 44, 56, 58, 64 AVdd CVdd PLLVdd Vdd Gnd ADC analog supply 2 Core logic power PLL supply 2 I/O ring power (#33 is to ADC only 2) Core, analog and I/O grounds 3
S S S S 3.3 0 S 1.8
1. This column is the nominal maximum for a given pin. Pins listed as 5 V can tolerate voltages up to 5 V (inputs have threshold voltages related to the 3V3 supply). 2. Pins #22, #28 and #33 should have separate supply lines from the digital supplies of the same voltage. 3. Decoupling capacitors should be used from every Gnd pin to its adjacent supply pin, with the capacitor as close as possible to the pins. Pin #26 is provided to allow the oscillator to be ringed.
8 Zarlink Semiconductor Inc.
ZL10210 2.0
2.1 2.1.1
* *
Data Sheet
Interfaces
2-wire Bus Host
The primary 2-wire bus serial interface uses pins: DATA1 (pin #10) serial data, the most significant bit is sent first. CLK1 (pin #9) serial clock.
The 2-wire bus address is determined by applying Vdd or Gnd to the SADD[4:0] pins. In CNIM evaluation applications, the 2-wire bus address is 0001 111 R/W with the pins connected as follows:
ADDR[7] ADDR[6] ADDR[5] SADD[4] Gnd ADDR[4] SADD[3] Vdd ADDR[3] SADD[2] Vdd ADDR[2] SADD[1] Vdd ADDR[1] SADD[0] Vdd
Not programmable Gnd Gnd
When the ZL10210 is powered up, the RESET pin 9 should be held low for at least 50 ms after Vdd has reached normal operation levels. As the RESET pin goes high, the logic levels on SADD[4:0] are latched as the 2-wire bus address. ADDR[0] is the R/W bit. The circuit works as a slave transmitter with the address lsb set high or as a slave receiver with the lsb set low. In receive mode, the first data byte is written to the RADD virtual register, which forms the register address. The RADD register takes an 8-bit value that determines which of 256 possible register addresses is written to by the following byte. Not all addresses are valid and many are reserved registers that must not be changed from their default values. Multiple byte reads or writes will auto-increment the value in RADD, but care should be taken not to access the reserved registers accidentally. Following a valid chip address, the 2-wire bus STOP command resets the RADD register to 00. If the chip address is not recognized, the ZL10210 will ignore all activity until a valid chip address is received. The 2-wire bus START command does NOT reset the RADD register to 00. This allows a combined 2-wire bus message, to point to a particular read register with a write command, followed immediately with a read data command. If required, this could next be followed with a write command to continue from the latest address. RADD would not be sent in this case. Finally, a STOP command should be sent to free the bus. When the 2-wire bus is addressed (after a recognized STOP command) with the read bit set, the first byte read out is the contents of register 00.
2.1.2
Tuner
The ZL10210 has two GPP (general purpose port) pins which are normally configured to provide a secondary 2-wire bus, allowing the main serial bus to be connected through to the tuner only when it is necessary to communicate with the tuner. This reduces the electrical noise seen by the tuner and improves the performance. The allocation of the pins is: pin 45 = CLK2 or GPP3; pin 46 = DATA2 or GPP2. Pass-through mode is selected by setting register Tuner_Ctl (0x56) [b0] = `1', otherwise, if this bit is `0', then there is no connection between the two serial buses. In this same register, bit [b2] must also be set to a `1' to enable the pins for serial use rather than as general purpose port pins. See also register GPP_Ctl address 0x55 for details of using these pins as GPPs.
9 Zarlink Semiconductor Inc.
ZL10210
2.1.3 Examples of 2-wire Bus Messages:
KEY: S P A Italics Start condition Stop condition Acknowledge ZL10210 output W R NA RADD Write (= 0) Read (= 1) NOT Acknowledge Register Address
Data Sheet
Write operation - as a slave receiver: S DEVICE ADDRESS W A RADD (n) A DATA (reg n) A DATA (reg n+1) A P
Read operation - ZL10210 as a slave transmitter: S DEVICE ADDRESS R A DATA (reg 0) A DATA (reg 1) A DATA (reg 2) NA P
Write/read operation with repeated start - ZL10210 as a slave transmitter:
S DEVICE ADDRESS W A RADD (n) A S DEVICE ADDRESS R A DATA (reg n) A DATA (reg n+1) NA P
2.1.4
Primary 2-wire Bus Timing
tBUFF
DATA1
Sr
P
tLOW
CLK1 P
t R
tF
S tHD;STAt t t HIGH t SU;DAT SU;STA HD;DAT
tSU;STO
Figure 5 - Primary 2-wire Bus Timing Where: S = Start Sr = Restart, i.e., start without stopping first P = Stop
10 Zarlink Semiconductor Inc.
ZL10210
Value Parameter CLK clock frequency (Primary) Bus free time between a STOP and START condition. Hold time (repeated) START condition. LOW period of CLK clock. HIGH period of CLK clock. Set-up time for a repeated START condition. Data hold time (when input). Data set-up time Rise time of both CLK and DATA signals. Fall time of both CLK and DATA signals, (100pF to ground). Set-up time for a STOP condition. Symbol Min. fCLK tBUFF tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tR tF tSU;STO Table 3 - Timing of 2-Wire Bus
1. If operating with an external 4 MHz clock, the serial clock frequency is reduced to 100 kHz maximum. 2. The rise time depends on the external bus pull up resistor. Loading prevents full speed operation.
Data Sheet
Unit Max. 400 1 kHz ns ns ns ns ns ns ns note 2 20 200 ns ns ns 0 200 200 1300 600 200 100 100
2.2 2.2.1
MPEG Data Output Header Format
188 byte packet output 184 Transport packet bytes
Transport Packet Header 4 bytes 0 TEI 1 0 0 0 1 1 1 1st byte 2nd byte
MDO[7]
MDO[0]
Figure 6 - DVB Transport Packet Header Byte
11 Zarlink Semiconductor Inc.
ZL10210
Data Sheet
After decoding the 188-byte MPEG packet, it is output on the MDO pins in 188 consecutive clock cycles. Additionally when the TEI_En bit in the MCLK_CTL register (0x77) is set high (default), the TEI bit of any uncorrectable packet will automatically be set to `1'. If TEI_En bit is low then TEI bit will not be changed (but note that if this bit is already 1, for example, due to a channel error which has not been corrected, it will remain high at output).
2.2.2
MPEG Data Output Signals
The MPEGEN bit in the CONFIG register must be set low to enable the MPEG data pins as outputs. The maximum movement in the packet synchronization byte position is limited to 1 output clock period. MOCLK will be a continuously running clock once symbol lock has been achieved, and is derived from the symbol clock. MOCLK is shown in Figure 7 with MOCLKINV = `1', the default state, see register 0x50. All output data and signals (MDO[7:0], MOSTRT, MOVAL & BKERR) change on the negative edge of MOCLK (MOCLKINV = 1) to present stable data and signals on the positive edge of the clock. A complete packet is output on MDO[7:0] on 188 consecutive clocks and the MDO[7:0] pins will remain low during the inter-packet gaps. MOSTRT goes high for the first byte clock of a packet. MOVAL goes high on the first byte of a packet and remains high until the last byte has been clocked out. BKERR goes low on the first byte of a packet where uncorrectable bytes are detected and will remain low until the last byte has been clocked out.
1st byte packet n MOCLKINV=1 MOCLK
188 byte packet n
1st byte packet n+1
MDO7:0
MOSTRT
MOVAL
BKERR
Tp
Ti
Figure 7 - MPEG Output Data Waveforms
2.2.3
MPEG Output Timing
Maximum delay conditions: Vdd = 3.0 V, CVdd = 1.62 V, Tamb = 85oC, Output load = 10 pF. Minimum delay conditions: Vdd = 3.6 V, CVdd = 1.98 V, Tamb = -40oC, Output load = 10 pF. MOCLK frequency = 45.06 MHz.
12 Zarlink Semiconductor Inc.
ZL10210
2.2.4 MOCLKINV = 1
Parameter Data output delay tD Setup Time tSU Hold Time tH Delay Conditions Maximum 3.0 7.0 7.0 Minimum 1.0 10.0 10.0 ns Units
Data Sheet
MOCLK MDO MOSTRT MOVAL BKERRB BKERR
}
tH
Delay Conditions Maximum 3.0 18.0 1.0 Minimum 1.0 20.0 0.2 ns Units
tD
tSU
Figure 8 - MPEG Timing - MOCLKINV = 1
2.2.5
MOCLKINV = 0
MDOSWAP = 0
Parameter Data output delay tD Setup Time tSU Hold Time tH
The hold time is better when MOCLKINV = 1, therefore this should be used if possible.
MOCLK MDO MOSTRT MOVAL BKERRB BKERR
}
tD
tSU tH
Figure 9 - MPEG Timing - MOCLKINV = 0
13 Zarlink Semiconductor Inc.
ZL10210 3.0
3.1
Data Sheet
Electrical Characteristics
Recommended Operating Condition
Parameter Symbol Min. Typ. Max. Units
Core power supply voltage Periphery power supply voltage Input clock frequency (note ) Crystal oscillator frequency CLK1 clock frequency (with 10 MHz or above) Ambient operating temperature
CVdd Vdd Fxt1 Fxt2 Fclk1
1.71 3.13 3.99 9.99 -40
1.8 3.3
1.89 3.47 27.01 16.01 400 85
V V MHz MHz kHz C
. When not using a crystal, XTI may be driven from an external source over the frequency range shown. . The maximum serial clock speed on the primary 2-wire bus is related to the input clock frequency and is limited to 100 kHz with a 4.0 MHz clock.
3.2
Absolute Maximum Ratings
Maximum Operating Conditions Parameter Power supply Voltage on input pins (5 V rated) Voltage on input pins (3.3 V rated) Voltage on input pins (1.8 V rated, e.g., XTI) Voltage on output pins (5 V rated) Voltage on output pins (3.3 V rated) Voltage on output pins (1.8 V rated, e.g., XTO) Storage temperature Operating ambient temperature Junction temperature ESD protection (human body model)
Note 1:
Symbol Vdd CVdd Vi Vi Vi Vo Vo Vo Tstg Top Tj
Min. -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -55 -40 4
Max 4.5 2.3 5.5 6.5 CVdd + 0.3 5.5 Vdd + 0.3 CVdd + 0.3 150 85 125
Unit V V V V V V V C C C kV
Stresses exceeding these listed under 'Absolute Ratings' may induce failure. Exposure to absolute maximum ratings for extended periods may reduce reliability. Functionality at or above these conditions is not implied.
14 Zarlink Semiconductor Inc.
ZL10210
3.3 Crystal Specification
Data Sheet
Parallel resonant fundamental frequency (preferred) 9.99 to 16.01 MHz. Tolerance over operating temperature range 25 ppm. Tolerance overall 50 ppm. Nominal load capacitance 30 pF. Equivalent series resistance <50
Figure 10 - Crystal Oscillator Circuit
3.3.1
Selection of External Components
The capacitor values used must ensure correct operation of the Pierce oscillator such that the total loop gain is greater than unity. Correct selection of the two capacitors is very important and the following method is recommended to obtain values for C1 and C2.
3.3.1.1
Loop Gain Equation
Although oscillation may still occur if the loop gain is just above 1, a loop gain of between 5 and 25 is optimum to ensure that oscillations will occur across all variations in temperature, process and supply voltage, and that the circuit will exhibit good start-up characteristics. A= Zin = Cout.gm Cin Cout + Cin Rf.Cin + 1 Zin + 1 Zo -1 - Equation 1 - Equation 2
1 (2..f.Cout)2.ESR
3.3.1.2
A Cin Cout Cpar Zo
List of Equation Parameters
total loop gain (between 5 and 25) C1 + Cpar C2 + Cpar parasitic capacitance associated with each oscillator pin (XTI and XTO). It consists of track capacitances, package capacitance and cell input capacitance. Normally Cpar 4 pF. 9.143 k - output impedance of amplifier at 1.8 V operation - typical
15 Zarlink Semiconductor Inc.
ZL10210
gm Rf ESR f 8.736mA/V - transconductance of amplifier at 1.8 V operation -typical 2.3M - internal feedback resistor maximum equivalent series resistance of crystal - given by crystal manufacturer () fundamental frequency of crystal (Hz)
Data Sheet
3.3.1.3
Calculating Crystal Power Dissipation
To calculate the power dissipated in a crystal the following equation can be used: Pc = Vpp2 8.Zin - Equation 3
Pc = power dissipated in crystal at resonant frequency (W) Vpp = maximum peak to peak output swing of amplifier is 1.8 V for all CVdd Zin = crystal network impedance (see Equation 2)
3.3.1.4
Capacitor Values
Using the loop gain limits (5 < A < 25), the maximum and minimum values for C1 and C2 can be calculated with Equation 4 below. Cin = Cout = 1 gm 2 1. A Rf Zo (2..f)2.ESR when: C1 = C2 = Cout - Cpar - Equation 4
Note: Equation 4 was derived from Equation 1 and Equation 2 using the premise that C1 = C2. Within these limits, any value for C1 and C2 can now be selected. Normally C1 and C2 are chosen such that the resulting crystal load capacitance CL (see Equation 5) is close to the crystal manufacturers recommended CL (standard values for CL are 15 pF, 20 pF and 30 pF). The crystal will then operate very near its specified frequency. CL = Cout . Cin Cout + Cin + Cpar12 - Equation 5
Cpar12 = parasitic capacitance between the XTI and XTO pins. It consists of the IC package's pin-to-pin capacitance (including any socket used) and the printed circuit board's track-to-track capacitance. Cpar12 2pF. If some frequency pulling can be tolerated, a crystal load capacitance different from the crystal manufacturer's recommended CL may be acceptable. Larger values of CL tend to reduce the influence of circuit variations and tolerances on frequency stability. Smaller values of CL tend to reduce startup time and crystal power dissipation. Care must however be taken that CL does not fall outside the crystal pulling range or the circuit may fail to start up altogether. It is also possible to quote CL to the crystal manufacturer who can then cut a crystal to order which will resonate, under the specified load conditions, at the desired frequency. Finally the power dissipation in the crystal must be checked. If Pc is too high C1 and C2 must be reduced. If this is not feasible C2 alone may be reduced. Unbalancing C1 and C2 will, however, require checking if the loop gain condition is still satisfied. This must be done using Equation 1. C2 Note: 2 > > 0.5 C1
16 Zarlink Semiconductor Inc.
ZL10210
3.3.1.5
*
Data Sheet
Oscillator/Clock Application Notes
On the printed circuit board, the tracks to the crystal and capacitors must be made as short as possible. Other signal tracks must not be allowed to cross through this area. The component tracks should preferably be ringed by a ground track connected to the chip ground (0 V) on adjacent pins either side of the crystal pins. It is also advisable to provide a ground plane for the circuit to reduce noise. External clock signals, applied to XTI and/or XTO, must not exceed the cell supply limits (i.e., 0 V and CVdd) and current into or out of XTI and/or XTO must be limited to less than 10mA to avoid damaging the cell's amplitude clamping circuit. An external, DC coupled, single ended square wave clock signal may be applied to XTI if OSCMODE = 0. To limit the current taken from the signal source a resistor should be placed between the clock source and XTI. The recommended value for this series resistor is 470 for a clock signal switching between 0 V and CVdd (1V8). The current the clock source needs to source/sink is then <1.9 mA. The XTO pin must be left unconnected in this configuration. AC coupling of a single ended external clock to XTI, with OSCMODE = 0, is not recommended. The duty cycle of the OSCOUT signal cannot be guaranteed in such a configuration. AC coupling of a single ended external clock to XTI, with OSCMODE = 1, is possible. It is recommended that the circuit shown in Figure 11 be used to correctly bias the oscillator inputs: The common-mode voltage VCM for XTI and XTO, (set by the 15 k and 22 k resistors) must be 800 mV < VCM < CVdd and the amplitude Vpp of the clock signal must be >400 mV.
*
*
* *
XTI
XTO 36k
Vdd
OSCMODE
External clock
10nF
100k 10nF 22k
Figure 11 - External Clocking via AC Coupling * External, differential clock signals may be applied to XTI and XTO if OSCMODE = 1. The common-mode voltage VCM for the differential clock signals must be 800 mV < VCM < CVdd, and the peak-to-peak signal amplitude Vpp must be >400 mV. It is recommended that differential clock signals have VCM = 1.0 V. For Vpp > 400 mV a resistor of >390 in series with XTI or XTO may be required to limit the current taken from or supplied to the clock sources.
17 Zarlink Semiconductor Inc.
ZL10210
3.4 Electrical Characteristics
Tamb = 25C CVdd = 1.8 V Vdd = 3.3 V
Data Sheet
Conditions (unless specified otherwise): DC Electrical Characteristics Parameter Core voltage Peripheral voltage Core current Peripheral current Total power Total power (stand-by) Total power (sleep) Output low level Output high level Output leakage Default settings
Conditions/Pin
Symbol CVdd Vdd CIdd Idd Ptot1
Min. 1.71 3.13
Typ. 1.8 3.3 120 2.2 223 2.55 0.10
Max. 1.89 3.47
Unit V V mA mA mW mW mW
ADCs powered down. MPEG outputs tri-stated Pin 20 = logic `1' & ADCs powered down 2, 6 or 12 mA per output (see section 1.3, Pin Description) 2, 6 or 12 mA per output Tri-state when off or open-drain when high All outputs except XTO, CLK1 & open-drain types. Excludes packaging contribution (~0.35pF) Open-drain outputs. Excludes packaging contribution (~0.35pF)
Ptot2 Ptot3 Vol Voh 2.4
0.4
V V
1 2.7
A pF
Output capacitance
3.3
pF
Input low level Input high level Input leakage Input capacitance Vin = 0 or Vdd Excludes packaging contribution (~0.35pF)
Vil Vih 2.0
0.8 1 1.5
V V A pF
18 Zarlink Semiconductor Inc.
ZL10210
AC Electrical Characteristics Parameter ADC Full-scale input single range (single-ended or differential) ADC analog input resistance ADC input common mode voltage level RF ADC Full-scale input single range (single-ended) RF ADC analog input resistance RF ADC input common mode voltage System clock frequency Input clock frequency (note Crystal oscillator frequency CLK1 clock frequency (with 10 MHz xtal or above) MPEG clock input frequency On pin #63 note
)
Data Sheet
Conditions/Pin Differential source is recommended Per input pin
Min.
Typ. 1.6 25 0.9 3.3 25 1.65
Max.
Unit Vpp k V Vpp k V
30.00 See Section 3.3.1.5 for details. See Section 3.3 for details 3.99 9.99
100 27.01 16.01 400 65
MHz MHz MHz kHz MHz
. Actually CVdd/2 . Actually Vdd/2 . When not using a crystal, XTI may be driven from an external source over the frequency range shown. . The maximum serial clock speed on the primary 2-wire bus is related to the input clock frequency and is limited to 100 kHz with a 4.0 MHz clock. . Must be calculated from the data input rate. . Must be lower than the system clock.
19 Zarlink Semiconductor Inc.
For more information about all Zarlink products visit our Web Site at
www.zarlink.com
Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively "Zarlink") is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink's conditions of sale which are available on request.
Purchase of Zarlink's I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright Zarlink Semiconductor Inc. All Rights Reserved.
TECHNICAL DOCUMENTATION - NOT FOR RESALE

▲Up To Search▲

Price & Availability of ZL10210

	To Download ZL10210 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .